Pipelined Adc Design and Enhancement Techniques pdf epub mobi txt 电子书下载 2026

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出版者:Springer ScienceþBusiness Media B.V.

作者:Imran Ahmed

出品人:

页数:225

译者:

出版时间:

价格:996.00

装帧:

isbn号码:9789048186518

丛书系列:

图书标签:

Analog
ADC
Circuits
ADC
Pipeline ADC
Analog Circuit Design
Mixed-Signal Circuit
High-Speed ADC
Low-Power ADC
Digital Calibration
Error Correction
Circuit Optimization
VLSI Design

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具体描述

Pipelined ADCs have seen a tremendous growth in innovation and scope over the

past few years. As such understanding both the basic concepts and the leading edge techniques required to realize pipelined ADCs which meet the challenging speciﬁcations of today’s market and applications is required. While pipelined ADCs are popular circuit blocks, beyond publications in periodicals there are only a few condensed resources which are dedicated to education in the area. This book aims to help bridge the gap with a thorough discussion of pipelined ADCs.

This book is targeted to both the beginner and expert looking to acquire

knowledge in pipelined ADCs. In the ﬁrst section of this book, a tutorial discussion

of several key design tradeoffs involved in designing a pipelined ADC is given. The

discussion is presented with sufﬁcient detail so as to allow those with only intro-

ductory knowledge of pipelined ADCs to quickly understand the limiting factors

which motivate research into methods which enhance the performance of pipelined ADCs. In the second half of this book a detailed overview and discussion of four state-of-the-art pipelined ADCs with silicon implementations and measured results is given. The innovations include: a technique to rapidly digitally correct gain +DAC errors in a pipelined ADC, an architecture to enable a single ADC to be

designed to achieve low power for a very wide range of sampling rates, a circuit

technique to eliminate front-end sample-and-holds in pipelined ADCs, and ﬁnally a

very low power pipelined ADC architecture based on capacitive charge pumps.

The innovations presented in this book provides several tools which can be of

great use to help a pipelined ADC designer deliver a design with good linearity,

broad application, and very low power.

《高性能数据采集系统：原理、架构与实践》本书旨在深入探讨现代数据采集（ADC）系统的设计原理、关键技术及其在各个领域中的应用。读者将通过本书全面了解ADC系统的核心概念，掌握不同类型ADC的优缺点，并学习如何根据具体需求选择和设计最优的ADC架构。核心内容概述：第一部分：数据采集系统基础数字信号处理导论：回顾信号的采样、量化和编码等基本概念，介绍采样定理在ADC设计中的重要性。 ADC基本原理与分类：详细阐述逐次逼近型ADC（SAR ADC）、流水线型ADC（Pipeline ADC）、Sigma-Delta ADC、闪速型ADC（Flash ADC）等主流ADC架构的工作原理。深入分析各自的性能指标，如采样速率、分辨率、功耗、非线性度等，并探讨其适用场景。 ADC性能指标详解：深入解析Integral Non-Linearity (INL)、Differential Non-Linearity (DNL)、Signal-to-Noise Ratio (SNR)、Signal-to-Noise and Distortion Ratio (SINAD)、Effective Number of Bits (ENOB) 等关键性能指标的定义、测量方法及其对系统整体性能的影响。模拟前端电路设计：介绍用于ADC信号调理的关键模拟电路模块，包括采样保持电路（S/H）、低噪声放大器（LNA）、滤波器、输入缓冲器等的设计考量与实现技术。第二部分：ADC架构深度解析 SAR ADC的设计细节：深入讲解SAR ADC的比较器设计、电容阵列（DAC）的实现与优化、数字校准技术等，并探讨其在高分辨率、低功耗应用中的潜力。 Sigma-Delta ADC的精髓：详细解析Sigma-Delta调制器（Modulator）的结构、噪声整形原理、高阶调制器的设计挑战。介绍数字滤波器（Decimator）在Sigma-Delta ADC中的作用与设计方法，重点关注高分辨率、高线性度应用。 Flash ADC与Twos-Complement ADC：分析Flash ADC的并行比较器结构、速度优势及其在高速采样应用中的局限性。介绍Twos-Complement ADC的工作原理和优缺点。混合信号集成：探讨ADC与其他模拟和数字模块（如PLL、DAC、DSP核心）的集成设计，以及由此带来的系统级挑战与优化策略。第三部分：ADC性能优化与应用噪声分析与抑制：系统性地分析ADC系统中各种噪声源（如热噪声、闪烁噪声、量化噪声、时钟抖动噪声），并提出有效的抑制策略，包括器件选择、电路布局、噪声滤波等。非线性度补偿技术：深入研究ADC的非线性度产生原因，介绍多种线性度校准与补偿技术，包括查找表（LUT）校准、增益和失调校准、以及针对特定ADC架构的非线性度修正方法。电源管理与低功耗设计：探讨ADC系统中的电源分配、去耦、以及低功耗设计技术，包括动态电压频率调整（DVFS）、睡眠模式、以及优化电路工作点等。时钟抖动对ADC性能的影响：分析时钟抖动对ADC采样精度的影响，介绍时钟信号的完整性要求，以及降低时钟抖动对ADC性能的影响的实用技术。第四部分：ADC在现代系统中的应用通信系统中的ADC：探讨ADC在软件定义无线电（SDR）、基站、移动设备等通信系统中的应用，重点关注其对带宽、动态范围和功耗的要求。医疗电子领域的ADC：分析ADC在医学影像设备（如CT、MRI）、生物信号采集（如ECG、EEG）、以及可穿戴健康监测设备中的关键作用，强调高精度、低功耗和生物兼容性。工业自动化与仪器仪表：介绍ADC在传感器接口、数据采集系统、示波器、频谱分析仪等仪器仪表中的应用，关注其在恶劣环境下的可靠性和精度。嵌入式系统与物联网（IoT）：探讨ADC在嵌入式系统和IoT设备中的角色，包括传感器数据采集、低功耗节点设计，以及如何在资源受限的环境下实现高效数据采集。先进ADC技术展望：简要介绍当前ADC技术的前沿研究方向，如更高速度、更高分辨率的ADC、模数混合信号SoC设计、以及在新兴应用中的潜在突破。本书适合通信、电子工程、计算机科学等领域的工程师、研究人员和高年级本科生、研究生阅读。通过学习本书，读者将能够深刻理解ADC的工作原理，熟练掌握ADC的设计与优化方法，并将其成功应用于各类高性能数据采集系统中。

作者简介

目录信息

1 Introduction ............................................................... 1
1.1 Overview ............................................................... 1
1.2 Chapter Outline ........................................................ 3
1.2.1 Section I: Pipelined ADC Design .............................. 3
1.2.2 Section II: Pipelined ADC Enhancement Techniques ......... 4
Part I Pipelined ADC Design
2 ADC Architectures ....................................................... 7
2.1 Overview ............................................................... 7
2.2 Factors Which Determine ADC Resolution and Linearity ............ 7
2.3 ADC Architectures ................................................... 11
2.4 ADC Figure-of-Merit ................................................. 12
2.5 Flash ADC ............................................................ 12
2.6 SARADC ............................................................. 14
2.7 Sub-sampling ......................................................... 16
2.8 Summary .............................................................. 17
3 Pipelined ADC Architecture Overview ................................ 19
3.1 Overview .............................................................. 19
3.2 Pipelined ADC Introduction .......................................... 19
3.3 Multiplying Digital to Analog Converter (MDAC) .................. 21
3.4 Opamp DC Gain Requirements ...................................... 23
3.5 Opamp Bandwidth Requirements .................................... 26
3.6 Thermal Noise Requirements ......................................... 28
3.7 MDAC Design: Capacitor Matching/Linearity ...................... 29
3.8 Error Correction in Pipelined ADCs: Relaxed Sub-ADC
Requirements ......................................................... 31
3.9 Sub-ADC Design: Comparator ....................................... 35
3.10 Front-End Sample-and-Hold ........................................ 36
3.11 Summary ............................................................. 38
4 Scaling Power with Sampling Rate in an ADC ........................ 39
4.1 Overview .............................................................. 39
4.2 ADC Power as a Function of Sampling Rate ........................ 39
4.3 Digital Versus Analog Power ......................................... 40
4.4 Weak Inversion Model: EKV ........................................ 42
4.5 Weak Inversion Issues: Mismatch .................................... 43
4.6 Current Scaling: Multiple Design Corners . . . ........................ 45
4.7 Current Scaling: Bias Point Sensitivity .............................. 45
4.8 Current Scaling: IR Drops ............................................ 46
4.9 Summary .............................................................. 48
5 State of the Art Pipelined ADC Design ................................ 49
5.1 Overview .............................................................. 49
5.2 Calibration in Pipelined ADCs ....................................... 49
5.2.1 Review of Error Sources ....................................... 50
5.2.2 Gain Error Correction ......................................... 50
5.2.3 DAC Error Correction ......................................... 52
5.2.4 Foreground Calibration ........................................ 52
5.2.5 Background Calibration ....................................... 53
5.2.6 Rapid Calibration of ADC Errors ............................. 54
5.3 Power Scalability with Respect to Sampling Rate ................... 56
5.4 Power Reduction Techniques in Pipelined ADCs .................... 56
5.4.1 Front-End S/H Removal ....................................... 56
5.4.2 Open-Loop Ampliﬁer Approach ............................... 58
5.4.3 Comparator Based Switched Capacitor Circuits .............. 60
5.5 Summary .............................................................. 61
Part II Pipelined ADC Enhancement Techniques
6 Rapid Calibration of DAC and Gain Errors in a Multi-bit
Pipeline Stage ............................................................ 65
6.1 Overview .............................................................. 65
6.2 Motivation ............................................................ 65
6.2.1 Why Are DAC Errors Important to Correct? ................. 66
6.3 Rapid DAC + Gain Calibration Architecture ........................ 66
6.3.1 Measurement of Missing Codes Due to DAC
and Gain Errors ................................................ 67
6.3.2 Correction of Missing Codes .................................. 68
6.3.3 Mismatch Between ADCs ..................................... 69
6.3.4 Simulation Results ............................................. 70
6.4 Circuit Implementation ............................................... 73
6.4.1 Front-End Sample-and-Hold ................................... 74
6.4.2 5-Bit Flash ADC ............................................... 75
6.4.3 4-Bit MDAC ................................................... 75
6.4.4 Backend Pipelined ADC ....................................... 77
6.4.5 Digital Calibration ............................................. 78
6.5 Testing ................................................................ 78
6.5.1 PCB ............................................................ 79
6.5.2 Test Setup ...................................................... 79
6.6 Measured Results ..................................................... 81
6.6.1 INL/DNL Plots ................................................ 81
6.6.2 SNDR/SFDR Plots ............................................. 81
6.6.3 Calibration Time ............................................... 82
6.7 Summary .............................................................. 84
7 A Power Scalable and Low Power Pipelined ADC .................... 85
7.1 Overview .............................................................. 85
7.2 Power Scalable Architecture ......................................... 85
7.3 Current Modulated Power Scaling (CMPS) . . ........................ 88
7.4 Current Switching Issues ............................................. 91
7.5 Hybrid Power Scaling ................................................ 92
7.6 Detailed Trigger Analysis ............................................ 93
7.7 Design of the Digital State Machine ................................. 97
7.8 Rapid Power-On Opamps ........................................... 100
7.8.1 Conventional Approach: Switched Bias Opamp ............. 100
7.8.2 Rapid Power-On Opamps Used in This Work ............... 101
7.8.3 Beneﬁts of Feedback Based Biasing: Increased Output
Resistance ..................................................... 104
7.8.4 Opamp Speciﬁcation/Characterization ....................... 105
7.9 Common Mode Feed Back (CMFB) for Rapid
Power-On Opamp ................................................... 109
7.10 Power Reduction Through Current Modulation .................. 111
7.10.1 Common Mode Feed Back (CMFB) for
Different Opamp Modes .................................. 112
7.11 Sample-and-Hold (S/H) ........................................... 113
7.12 1.5-bit MDAC ..................................................... 114
7.13 Sub-ADC Comparators ............................................ 114
7.14 Bias Circuits ....................................................... 115
7.15 Non-overlapping Clock Generator ................................ 116
7.16 Reference voltages ................................................ 117
7.17 Digital Error Correction ........................................... 118
7.18 Experimental Implementation: PCB .............................. 118
7.19 Experimental Implementation: Test Setup . . ...................... 118
7.20 Measured Results .................................................. 120
7.21 Current Scaled Power ............................................. 121
7.21.1 Power Reduction Mode: Static Accuracy ................. 127
7.21.2 Power Scalable ADC: Current Scaling ................... 131
7.22 Power Scalable ADC: Power Scaling Using CMPS .............. 137
7.23 Summary ........................................................... 144
8 A Sub-sampling ADC with Embedded Sample-and-Hold ........... 147
8.1 Overview ............................................................ 147
8.2 Motivation .......................................................... 147
8.3 Embedded S/H Technique .......................................... 148
8.4 Circuit Implementation ............................................. 151
8.4.1 ADC Architecture ............................................ 151
8.4.2 Rapid Power-On Opamp ...................................... 152
8.4.3 Generation of Delayed Clock F2D ........................... 153
8.5 Test Setup: PCB .................................................... 155
8.6 Test Setup: Equipment .............................................. 156
8.7 Measured Results ................................................... 156
8.7.1 SNDR Versus Input Frequency ............................... 157
8.7.2 Power Versus Sampling Rate ................................. 158
8.7.3 Tdelay Versus Settling Time: Robustness of Technique ...... 159
8.8 Summary ............................................................ 160
9 A Capacitive Charge Pump Based Low Power
Pipelined ADC .......................................................... 163
9.1 Overview ............................................................ 163
9.2 Motivation .......................................................... 164
9.3 Architecture: Capacitive Charge Pump Based Gain ............... 164
9.4 Effect of Parasitic Capacitors ....................................... 168
9.5 Unity Gain Buffer Topology ....................................... 170
9.5.1 Linearity of Source Follower in a Sampled System ......... 175
9.5.2 Signal Swing of Source Follower ............................ 176
9.6 Noise Analysis of Capacitive Charge Pump Based MDAC ....... 177
9.7 Calibration of Pipeline Stages ...................................... 181
9.7.1 Foreground Calibration in Detail ............................. 181
9.8 Theoretical Power Savings ......................................... 183
9.9 Design Speciﬁcations ............................................... 185
9.10 Circuit Design ..................................................... 186
9.10.1 ADC Top Level Topology ................................ 186
9.10.2 Front-End Sample-and-Hold .............................. 187
9.10.3 MDAC and Unity Gain Ampliﬁer . . ...................... 187
9.10.4 Sub-ADC .................................................. 189
9.10.5 Digital State Machine ..................................... 190
9.10.6 Analog Test-Mux .......................................... 190
9.11 Testing ............................................................. 191
9.11.1 PCB ........................................................ 191
9.11.2 Test Setup ................................................. 191
9.12 Measured Results .................................................. 193
9.12.1 Measured ADC SNDR Variation . . . ...................... 194
9.12.2 ADC FFTs ................................................. 196
9.12.3 INL/DNL plots ............................................ 199
9.13 Summary ........................................................... 199
10 Summary ................................................................ 201
10.1 Summary ........................................................... 201
References .................................................................... 203
Index .......................................................................... 209
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