The book covers topics such as cell timing and power modeling; interconnect modeling and analysis, delay calculation, crosstalk, noise and the chip timing verification using static timing analysis. For each of these topics, the book provides a theoretical background as well as detailed examples to elaborate the concepts. The static timing analysis topics covered start from verification of simple blocks useful for a beginner to this field. The topics then extend to complex nanometer designs with in-depth treatment of concepts such as modeling of on-chip variation, clock gating, half-cycle paths, as well as timing of source-synchronous interfaces such as DDR. The impact of crosstalk on timing and noise is covered as is the usage of hierarchical design methodology. This book addresses CMOS logic gates, cell library, timing arcs, waveform slew, cell capacitance, timing modeling, interconnect parasitics and coupling, pre- and post-layout interconnect modeling, delay calculation, specification of timing constraints for analysis of internal paths as well as IO interfaces. Advanced modeling and analysis concepts such as controlled current source timing and noise models for nanometer technologies, power modeling including active and leakage power, crosstalk timing and crosstalk glitch calculation, verification of half-cycle and multi-cycle paths, false paths, synchronous interfaces are also covered.
具體描述
讀後感
評分
評分
評分
評分
用戶評價
重讀無數遍瞭，再讀一遍
评分重讀無數遍瞭，再讀一遍
评分算是STA方麵的九陰真經瞭吧。
评分當時作為做綜閤的一本參考進行瞭閱讀 講的還是比較細比較清楚 內容適閤於初學者 可以跟design compiler的user guide配閤一起看
评分對STA的瞭解就是從這本書開始，隻可惜沒有吃透。。
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