Chapter 1 Components and Systems 1.1 WIRE 1.1.1 Skin Effect 1.1.2 Straight-Wire Inductors 1.2 RESISTORS 1.2.1 Resistor Equivalent Circuit 1.3 CAPACITORS 1.3.1 Parallel-Plate Capacitor 1.3.2 Real-World Capacitors 1.3.3 Capacitor Types 1.4 INDUCTORS 1.4.1 Real-World Inductors 1.4.2 Single-Layer Air-Core Inductor Design 1.4.3 Magnetic-Core Materials 1.5 TOROIDS 1.5.1 Core Characteristics 1.5.2 Powdered Iron vs. Ferrite 1.6 TOROIDAL INDUCTOR DESIGN 1.7 PRACTICAL WINDING HINTSChapter 2 Resonant Circuits 2.1 SOME DEFINITIONS 2.2 RESONANCE（LOSSLESS COMPONENTS） 2.3 LOADED Q 2.3.1 Effect of Rs and RL on the Loaded Q 2.3.2 The Effect of Component Q on Loaded Q 2.4 INSERTION LOSS 2.5 IMPEDANCE TRANSFORMATION 2.6 COUPLING OF RESONANT CIRCUITS 2.6.1 Capacitive Coupling 2.6.2 Inductive Coupling 2.6.3 Active Coupling 2.7 SUMMARYChapter 3 Filter Design 3.1 BACKGROUND 3.2 MODERN FILTER DESIGN 3.3 NORMALIZATION AND THE LOW-PASS PROTOTYPE 3.4 FILTER TYPES 3.4.1 The Butterworth Response 3.4.2 The Chebyshev Response 3.4.3 The Bessel Filter 3.5 FREQUENCY AND IMPEDANCE SCALING 3.6 HIGH-PASS FILTER DESIGN 3.7 THE DUAL NETWORK 3.8 BANDPASS FILTER DESIGN 3.9 SUMMARY OF THE BANDPASS FILTER DESIGN PROCEDURE 3.10 BAND-REJECTION FILTER DESIGN 3.11 THE EFFECTS OF FINITE QChapter 4 Impedance Matching 4.1 BACKGROUND 4.2 THE L NETWORK 4.3 DEALING WITH COMPLEX LOADS 4.4 THREE-ELEMENT MATCHING 4.4.1 The Pi Network 4.4.2 The T network 4.5 LOW-Q OR WlDEBAND MATCHING NETWORKS 4.6 THE SMITH CHART 4.6.1 Smith Chart Construction 4.6.2 Basic Smith Chart Tips 4.6.3 Plotting Impedance Values 4.6.4 Impedance Manipulation on the Chart 4.6.5 Conversion of Impedance to Admittance 4.6.6 Admittance Manipulation on the Chart 4.7 IMPEDANCE MATCHING ON THE SMITH CHART 4.7.1 Two-Element Matching 4.7.2 Three-Element Matching 4.7.3 Multi-Element Matching 4.8 SOFTWARE DESIGN TOOLS 4.8.1 Smith Chart Tools 4.8.2 Integrated Design Tools 4.9 SUMMARYChapter 5 The Transistor at Radio Frequencies 5.1 RF TRANSISTOR MATERIALS 5.2 THE TRANSISTOR EQUIVALENT CIRCUIT 5.2.1 Input Impedance 5.2.2 Output Impedance 5.2.3 Feedback Characteristics 5.2.4 Gain 5.2.5 Transistor as a Switch 5.2.6 MEMs as a Switch 5.3 Y PARAMETERS 5.3.1 The Transistor as a Two-Port Network 5.3.2 Two-Port Y Parameters 5.4 S PARAMETERS 5.4.1 Transmission Line Background 5.4.2 S Parameters and the Two-Port Network 5.5 UNDERSTANDING RF TRANSISTOR DATA SHEETS 5.6 SUMMARYChapter 6 Small-Signal RF Amplifier Design 6.1 SOME DEFINITIONS 6.2 TRANSISTOR BIASING 6.3 DESIGN USING Y PARAMETERS 6.3.1 Stability Calculations 6.3.2 Maximum Available Gain 6.3.3 Simultaneous Conjugate Matching（Unconditionally Stable Transistors） 6.3.4 Transducer gain 6.3.5 Designing with Potentially Unstable Transistors 6.4 DESIGN USING S PARAMETERS 6.4.1 Stability 6.4.2 Maximum Available Gain 6.4.3 Simultaneous Conjugate Match（Unconditionally Stable Transistors） 6.4.4 Transducer Gain 6.4.5 Design for a Specified Gain 6.4.6 Stability Circles 6.4.7 Design for Optimum Noise Figure 6.4.8 Design ExampleChapter 7 RF（Large Signal）Power Amplifiers 7.1 RF POWER TRANSISTOR CHARACTERISTICS 7.1.1 The RF Power Transistor Data Sheet 7.2 TRANSISTOR BIASING 7.2.1 Class-A Amplifiers and Linearity 7.2.2 Class-B Power Amplifiers 7.2.3 Class-C Power Amplifiers 7.3 RF SEMICONDUCTOR DEVICES 7.3.1 Monolithic Microwave Integrated Circuits（MMIC） 7.4 POWER AMPLIFIER DESIGN 7.4.1 Optimum Collector Load Resistance 7.4.2 Driver Amplifiers and Interstage Matching 7.5 MATCHING TO COAXIAL FEEDLINES 7.6 AUTOMATIC SHUTDOWN CIRCUITRY 7.7 BROADBAND TRANSFORMERS 7.7.1 Power Splitters 7.7.2 Power Combiners 7.8 PRACTICAL WINDING HINTS 7.9 SUMMARYChapter 8 RF Front-End Design 8.1 HIGHER LEVELS OF INTEGRATION 8.2 BASIC RECEIVER ARCHITECTURES 8.2.1 AM Detector Receivers 8.2.2 TRF Receiver 8.2.3 Direct-Conversion Receiver 8.2.4 Superheterodyne Receivers 8.2.5 Front-End Amplifiers 8.2.6 Selectivity 8.3 ADC'S EFFECT ON FRONT-END DESIGN 8.4 SOFTWARE DEFINED RADIOS 8.5 CASE STUDY—MODERN COMMUNICATION RECEIVER 8.5.1 IF Amplifier DesignChapter 9 RF Design Tools 9.1 DESIGN TOOL BASICS 9.2 DESIGN LANGUAGES 9.2.1 Verilog 9.2.2 Verilog-AMS 9.2.3 Verilog-A 9.2.4 SystemVerilog 9.2.5 VHDL 9.2.6 VHDL-AMS 9.2.7 VHDL-AMS/FD 9.2.8 VHDL-RF/MW 9.2.9 C/C++ 9.2.10 SystemC 9.2.11 MATLAB/RF Toolbox/Simulink 9.2.12 SPICE 9.3 RFIC DESIGN FLOW 9.3.1 System Design 9.3.2 Circuit Design 9.3.3 Circuit Layout 9.3.4 Parasitic Extraction 9.3.5 Full-Chip Verification 9.4 RFIC DESIGN FLOW EXAMPLE 9.4.1 HDL Multi-Level Simulation 9.4.2 Block Circuit Design 9.4.3 Physical Implementation 9.4.4 Parasitic Extraction 9.4.5 Calibrated Models 9.5 SIMULATION EXAMPLE 1 9.6 SIMULATION EXAMPLE 2 9.7 MODELING 9.7.1 Modeling Issues 9.8 PCB DESIGN 9.8.1 The Flow 9.8.2 PCB Design Tools 9.9 PACKAGING 9.9.1 Options 9.9.2 Design Solutions 9.10 CASE STUDY 9.10.1 System-Level Transceiver Design 9.10.2 Circuit-Level Receiver Design 9.10.3 LNA Design 9.10.4 Device Characterization 9.10.5 Circuit Design 9.10.6 Down-Converter Circuit Design 9.10.7 Transmitter Circuit Design 9.10.8 Up-Converter Design 9.10.9 Mixer Design 9.10.10 PA Design 9.10.11 PA Device Characterization 9.10.12 PA Circuit Design 9.11 SUMMARYAppendix A RF and AntennasAppendix B Vector AlgebraBibliography
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