Networks on Chip presents a variety of topics, problems and approaches with the common theme to systematically organize the on-chip communication in the form of a regular, shared communication network on chip, an NoC for short.

As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation.

The book is organized in three parts. The first deals with system design and methodology issues. The second presents problems and solutions concerning the hardware and the basic communication infrastructure. Finally, the third part covers operating system, embedded software and application. However, communication from the physical to the application level is a central theme throughout the book.

The book serves as an excellent reference source and may be used as a text for advanced courses on the subject.

Axel Jantsch received a Dipl.Ing. (1988) and a Dr. Tech. (1992) degree from the Technical University Vienna. Between 1993 and 1995 he received the Alfred Schrödinger scholarship from the Austrian Science Foundation as a guest researcher at the Royal Institute of Technology (KTH). From 1995 through 1997 he was with Siemens Austria in Vienna as a system validation engineer. Since 1997 he is Associate Professor at KTH, since 2000 he is Docent, since December 2002 he is full professor in Electronic System Design.

A. Jantsch has published over 150 papers in international conferences and journals and one book in the areas of VLSI design and synthesis, system level specification, modeling and validation, HW/SW codesign and cosynthesis, reconfigurable computing and networks on chip. He has served on a number of technical program committees of international conferences such as FDL, DATE, CODES+ISSS, SOC, and NOCS and others. He has been TPC chair of SSDL/FDL 2000, TPC cochair of CODES+ISSS 2004 and general chair of CODES+ISSS 2005. Since December 2002 he is Subject Area Editor for the Journal of System Architecture.

From January 1999 till December 2002 he has been program manager of the SSF funded research program Integrated Electronic Systems involving a total number of 50 Ph.D. students at four Universities. At the Royal Institute of Technology A. Jantsch is heading a number of research projects involving a total number of 10 Ph.D. students, in two main areas: System Modeling and Networks on Chip.