<P style="MARGIN: 0px">Every day, companies call upon their signal integrity engineers to make difficult decisions about design constraints and timing margins. Can I move these wires closer together? How many holes can I drill in this net? How far apart can I place these chips? Each design is unique: there&rsquo;s no single recipe that answers all the questions. Today&rsquo;s designs require ever greater precision, but design guides for specific digital interfaces are by nature conservative. Now, for the first time, there&rsquo;s a complete guide to timing analysis and simulation that will help you manage the tradeoffs between signal integrity, performance, and cost. </P> <P style="MARGIN: 0px"> </P> <P style="MARGIN: 0px">Writing from the perspective of a practicing SI engineer and team lead, Greg Edlund of IBM presents deep knowledge and quantitative techniques for making better decisions about digital interface design. Edlund shares his insights into how and why digital interfaces fail, revealing how fundamental sources of pathological effects can combine to create fault conditions. You won&rsquo;t just learn Edlund&rsquo;s expert techniques for avoiding failures: you&rsquo;ll learn how to develop the right approach for your own projects and environment. </P> <P style="MARGIN: 0px"> </P> <P style="MARGIN: 0px">Coverage includes</P> <P style="MARGIN: 0px">&bull; Systematically ensure that interfaces will operate with positive timing margin over the product&rsquo;s lifetime&ndash;without incurring excess cost </P> <P style="MARGIN: 0px">&bull; Understand essential chip-to-chip timing concepts in the context of signal integrity</P> <P style="MARGIN: 0px">&bull; Collect the right information upfront, so you can analyze new designs more effectively</P> <P style="MARGIN: 0px">&bull; Review the circuits that store information in CMOS state machines&ndash;and how they fail</P> <P style="MARGIN: 0px">&bull; Learn how to time common-clock, source synchronous, and high-speed serial transfers</P> <P style="MARGIN: 0px">&bull; Thoroughly understand how interconnect electrical characteristics affect timing: propagation delay, impedance profile, crosstalk, resonances, and frequency-dependent loss</P> <P style="MARGIN: 0px">&bull; Model 3D discontinuities using electromagnetic field solvers</P> <P style="MARGIN: 0px">&bull; Walk through four case studies: coupled differential vias, land grid array connector, DDR2 memory data transfer, and PCI Express channel</P> <P style="MARGIN: 0px">&bull; Appendices present a refresher on SPICE modeling and a high-level conceptual framework for electromagnetic field behavior</P> <P style="MARGIN: 0px">Objective, realistic, and practical, this is the signal integrity resource engineers have been searching for.</P> <P style="MARGIN: 0px"> </P> <P style="MARGIN: 0px">Preface xiii</P> <P style="MARGIN: 0px">Acknowledgments xvi</P> <P style="MARGIN: 0px">About the Author xix</P> <P style="MARGIN: 0px">About the Cover xx</P> <P style="MARGIN: 0px"> </P> <P style="MARGIN: 0px">Chapter 1: Engineering Reliable Digital Interfaces 1</P> <P style="MARGIN: 0px">Chapter 2: Chip-to-Chip Timing 13</P> <P style="MARGIN: 0px">Chapter 3: Inside IO Circuits 39</P> <P style="MARGIN: 0px">Chapter 4: Modeling 3D Discontinuities 73</P> <P style="MARGIN: 0px">Chapter 5: Practical 3D Examples 101</P> <P style="MARGIN: 0px">Chapter 6: DDR2 Case Study 133</P> <P style="MARGIN: 0px">Chapter 7: PCI Express Case Study 175</P> <P style="MARGIN: 0px"> </P> <P style="MARGIN: 0px">Appendix A: A Short CMOS and SPICE Primer 209</P> <P style="MARGIN: 0px">Appendix B: A Stroll Through 3D Fields 219</P> <P style="MARGIN: 0px"> </P> <P style="MARGIN: 0px">Endnotes 233</P> <P style="MARGIN: 0px">Index 235</P> <P style="MARGIN: 0px"> </P>